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Altera_Forum's avatar
Altera_Forum
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16 years ago

SOPC, Custom IP (Pass through) problem

Hi Everybody,

I have quartus 8.0 running on cyclone iii Board with bitec's hsmc dvi daughterboard on it.

I have clocked video input (1080p60 dvi input) and clocked video output (1080p60 dvi output). I want to add a dummy component in between my input and output.

At the beginning it will just pass through whatever comes by it, later on I am planning to do some easy XORing operations on the frame I am receiving.

What I did was, I clicked on "Create new component" and used different templates to start with such as Avalon M-M Slave/Master, Avalon St-Sink/Source and added all the signals to it like, clk, reset, data, ready, valid, starofpacket, endofpacket.

Regardless of which template I use, it always gives me the same error message : "the connection point has only some of the required packet signals"

I am a newbie, so I am obviously forgetting to add some signals which are necessary for my custom component to communicate with Clocked video in an out but I don't know what I am missing.

Can someone please guide me ?

Thank you so much in advance ,

Tyler

PS:I don't have the vhdl or verilog code for my custom component.

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    formjk is correct. The empty signal is the problem. However, it's not your fault. The Video IP cores do not use the empty signal, but SoPC builder expects it to be there for everything else. It's actually called out in the Errata.

    You can get around it by:

    1 - Don't create the empty signal for your custom core. When you want to create the core, hold the <Shift> key as you click create.

    2 - Do create the empty signal. In which case you'll get an error in SoPC builder when you connect up the component. Hold the <Shift> key when you click the generate button in SoPC builder.

    3 - Upgrade to 8.1 or 9.0. Altera fixed the problem in 8.1.

    Jake

    --- Quote End ---

    Hi Jake,

    I have one question, if you can clarify.

    I have few custom components in my SOPC. I m using Quartus 8.0.

    and untill now i was using the second option, holding the CTRL key while generating SOPC system.

    I tried with the first method, " dont create the empty signal and press CTRL while creating the component ".

    May be i am not following the correct steps, but how we can do that, not creating the empty signal in the component and getting the custom component.

    It would be helpful, if you can tell me the steps. As if there are no erros in SOPC, then it would be very helpful to me as i want to use C2H accelaration, if possible, without upgrading to 8.1 or 9.0.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks again Jake and formjk.

    I am working on my design running it on Quartus II 9.0

    Once I am done with creating my "pass through" component and doing the right pin connections and everything, I will bug you guys with some extra questions on XORing operation I believe

    Have a good weekend both of you :)

    Tyler
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    I can't thank you enough, Jake. You saved me, big time :)

    It worked smoothly. I have couple of extra questions if you or anybody else have time to answer.

    1)If possible, can you take a look at the screenshots and tell me if my component misses any signals that is necessary to work in between with clocked video input and output ?

    2) Can you guide me about where to start writing the XOR operation verilog/vhdl code and where to do the actual writing ?

    What should be taken to consideration and etc.

    I want to XOR the values of some of the pixels of my input screen and send it to the output screen. And,I am planning to do this operation in my "custom component".

    3) I know that is normal to get error messages while compiling after adding a dummy component but I am getting the following error message in Quartus after SOPC is done with generating. If possible, can you tell me the actual reason for that ?

    "error: block or symbol of type sopc_top and instance "inst" overlaps another pin, block, or symbol"

    Thank you again,

    Tyler

    --- Quote End ---

    Where is Image buffer? Image buffer is required for many video processing

    pipelines in which the input and output images are unsynchronised. (up/down scaling or image combining/blending).The input video stream is synchronised to the local pipeline video clock by means of triple frame buffer. The output signal is then streamed to the output port through the CVO component.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    muclear,

    I thought frame buffer was only necessary if you wanted to do some manipulation with the frame and that the CVI and CVO would be synchronized as long as you connect them to the same clock source. Then I read in one of the articles saying that I would need the frame buffer for synchronization problem, too. formjk and jakobjones also suggested that as well.

    Thanks for the warning.

    Today I will add the frame buffer into my project again and see how it will turn out.

    Tyler