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I can't thank you enough, Jake. You saved me, big time :)
It worked smoothly. I have couple of extra questions if you or anybody else have time to answer.
1)If possible, can you take a look at the screenshots and tell me if my component misses any signals that is necessary to work in between with clocked video input and output ?
2) Can you guide me about where to start writing the XOR operation verilog/vhdl code and where to do the actual writing ?
What should be taken to consideration and etc.
I want to XOR the values of some of the pixels of my input screen and send it to the output screen. And,I am planning to do this operation in my "custom component".
3) I know that is normal to get error messages while compiling after adding a dummy component but I am getting the following error message in Quartus after SOPC is done with generating. If possible, can you tell me the actual reason for that ?
"
error: block or symbol of type sopc_top and instance "inst" overlaps another pin, block, or symbol"
Thank you again,
Tyler
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Where is Image buffer? Image buffer is required for many video processing
pipelines in which the input and output images are unsynchronised. (up/down scaling or image combining/blending).The input video stream is synchronised to the local pipeline video clock by means of triple frame buffer. The output signal is then streamed to the output port through the CVO component.
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