SOPC, Custom IP (Pass through) problem

have you added "empty" signal ?

Also, i am not sure if you can create a component without a verilog/vhdl code.

may be as of now you can just create a verilog/vhdl module with just the port declaration and no logic inside.

formjk is correct. The empty signal is the problem. However, it's not your fault. The Video IP cores do not use the empty signal, but SoPC builder expects it to be there for everything else. It's actually called out in the Errata.

You can get around it by:

1 - Don't create the empty signal for your custom core. When you want to create the core, hold the <Shift> key as you click create.

2 - Do create the empty signal. In which case you'll get an error in SoPC builder when you connect up the component. Hold the <Shift> key when you click the generate button in SoPC builder.

3 - Upgrade to 8.1 or 9.0. Altera fixed the problem in 8.1.

Jake

Thank you formjk and Jake for your clear and fast responses. I did what you guys told me but SOPC doesn't allow me to generate. it says "Error: Generation skipped because the system has validation errors."

I am adding the screenshots of what I have been doing so far.

Basically I added Avalon Streaming Source and Avalon Streaming Sink for my custom component in order to be able to handle the high throughput of clocked video input and output.

I am not entirely sure if I am doing everything correctly, can you guys double check my design through the screenshots and let me know if there is any part that is not compatible for whatever reason ?

I would highly appreciate that.

PS: Once again my goal is first creating a pass through component between DVI clocked video input an DVI clocked video output. Once the SOPC generates I think I should start writing the verilog code to do the XORing operation.

Thanks a lot in advance,

Tyler

As I said before, you have to hold the <Shift> key while you click the "Generate" button to override the errors.

Jake

My appologies. It's the <Ctrl> key.

Jake

I can't thank you enough, Jake. You saved me, big time :)

It worked smoothly. I have couple of extra questions if you or anybody else have time to answer.

1)If possible, can you take a look at the screenshots and tell me if my component misses any signals that is necessary to work in between with clocked video input and output ?

2) Can you guide me about where to start writing the XOR operation verilog/vhdl code and where to do the actual writing ?

What should be taken to consideration and etc.

I want to XOR the values of some of the pixels of my input screen and send it to the output screen. And,I am planning to do this operation in my "custom component".

3) I know that is normal to get error messages while compiling after adding a dummy component but I am getting the following error message in Quartus after SOPC is done with generating. If possible, can you tell me the actual reason for that ?

"error: block or symbol of type sopc_top and instance "inst" overlaps another pin, block, or symbol"

Thank you again,

Tyler

1 - No your component looks fine.

2 - There are two methods...

a) The code for the component resides inside the component and inside your SoPC system. This is the most common method. What you do is actually write your module first. Then use the component editor in SoPC builder to create a new component and point it to your Verilog/VHDL code as a source file. You'll have to properly assign the ports on your module to corresponding interfaces in the component's signals list.

b) The code for the component resides outside SoPC builder. In this case (which is what you have now), SoPC builder simply exports the ports you've called out for your component (in your case it's the Avalon streaming interface signals for poth the sink and source interfaces. These will be the "valid","ready","data","startofpacket", and "endofpacket" signals. If you wish to use this method then you can place your code wherever you want and simply connect to the ports of the SoPC module.

3- I'm not sure why you are getting this error but it must have something to do with the way you are using Quartus and/or SoPC builder. My recommended approach is not to use the symbol files. I prefer to do the entire project in source code (Verilog for me). You must have two modules with the same name. Did you per chance name your SoPC system the same as your top level project file. If so, that's probably the issue. You can only have one module with the same name.

Jake

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I can't thank you enough, Jake. You saved me, big time :)

It worked smoothly. I have couple of extra questions if you or anybody else have time to answer.

1)If possible, can you take a look at the screenshots and tell me if my component misses any signals that is necessary to work in between with clocked video input and output ?

2) Can you guide me about where to start writing the XOR operation verilog/vhdl code and where to do the actual writing ?

What should be taken to consideration and etc.

I want to XOR the values of some of the pixels of my input screen and send it to the output screen. And,I am planning to do this operation in my "custom component".

3) I know that is normal to get error messages while compiling after adding a dummy component but I am getting the following error message in Quartus after SOPC is done with generating. If possible, can you tell me the actual reason for that ?

"error: block or symbol of type sopc_top and instance "inst" overlaps another pin, block, or symbol"

Thank you again,

Tyler

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Hi,

may be the path of your project is causing this error.

You have stored your project on desktop.. which has "C:\Documents and Settings\.. " .. spaces in the path.

Store your project on some of the drive, and make sure the folder name doesn't have any space.