SOPC, Custom IP (Pass through) problem

1 - No your component looks fine.

2 - There are two methods...

a) The code for the component resides inside the component and inside your SoPC system. This is the most common method. What you do is actually write your module first. Then use the component editor in SoPC builder to create a new component and point it to your Verilog/VHDL code as a source file. You'll have to properly assign the ports on your module to corresponding interfaces in the component's signals list.

b) The code for the component resides outside SoPC builder. In this case (which is what you have now), SoPC builder simply exports the ports you've called out for your component (in your case it's the Avalon streaming interface signals for poth the sink and source interfaces. These will be the "valid","ready","data","startofpacket", and "endofpacket" signals. If you wish to use this method then you can place your code wherever you want and simply connect to the ports of the SoPC module.

3- I'm not sure why you are getting this error but it must have something to do with the way you are using Quartus and/or SoPC builder. My recommended approach is not to use the symbol files. I prefer to do the entire project in source code (Verilog for me). You must have two modules with the same name. Did you per chance name your SoPC system the same as your top level project file. If so, that's probably the issue. You can only have one module with the same name.

Jake