SOPC Builder and nios ii help

If you have a specific problem then please post it here and I'm sure that the fine folks on this forum will pitch in with advice. If you want someone to do your homework then you're probably out of luck.

Mark.

thanks for the reply...

i tried running the code but am getting the error as follows

make -s all includes

Compiling LCD.c...

Compiling Test.c...

Compiling toplevel.c...

../toplevel.c: In function `ethernet_interrupts':

../toplevel.c:81: error: `DATA_IN_BASE' undeclared (first use in this function)

../toplevel.c:81: error: (Each undeclared identifier is reported only once

../toplevel.c:81: error: for each function it appears in.)

../toplevel.c:83: error: `DATA_TYPE_BASE' undeclared (first use in this function)

../toplevel.c:85: error: `DATA_ACK_BASE' undeclared (first use in this function)

../toplevel.c: In function `main':

../toplevel.c:206: error: `CPU_IP_READY_BASE' undeclared (first use in this function)

../toplevel.c:209: error: `CPU_IP_MAC_H_BASE' undeclared (first use in this function)

../toplevel.c:210: error: `CPU_IP_MAC_L_BASE' undeclared (first use in this function)

../toplevel.c:226: error: `CPU_IP_LENGTH_BASE' undeclared (first use in this function)

../toplevel.c:228: error: `CPU_IP_INDEX_BASE' undeclared (first use in this function)

../toplevel.c:230: error: `CPU_IP_DATA_BASE' undeclared (first use in this function)

../toplevel.c:237: error: `CPU_IP_DONE_BASE' undeclared (first use in this function)

../toplevel.c:245: error: `CPU_ARP_READY_BASE' undeclared (first use in this function)

../toplevel.c:248: error: `CPU_ARP_MAC_H_BASE' undeclared (first use in this function)

../toplevel.c:249: error: `CPU_ARP_MAC_L_BASE' undeclared (first use in this function)

../toplevel.c:266: error: `CPU_ARP_INDEX_BASE' undeclared (first use in this function)

../toplevel.c:268: error: `CPU_ARP_DATA_BASE' undeclared (first use in this function)

../toplevel.c:276: error: `CPU_ARP_DONE_BASE' undeclared (first use in this function)

../toplevel.c:170: warning: unused variable `TXT_INIT'

make: *** [obj/toplevel.o] Error 1

Build completed in 39.094 seconds

Hi,

Those *_BASE constants are names derived from your SOPC project created in SOPC builder and are define in the system.h include file that gets created in the NIOS library directory for the project. Find the system.h file and see what they've actually been called. It could be that you inadvertently renamed the blocks in your SOPC design.

For example, your errors tell me that it's expecting you to have a SOPC block called DATA_IN, one called DATA_TYPE, etc. but maybe you named them MY_DATA_IN. Just change the references in the C code (toplevel.c) to match what the SOPC blocks are actually called.

Mark.

Thanks Mark

I've got another issue, while adding my top level variables in SOPC (so as to get them

in system.h while building my hello_led.c in NIOS II), i'm facing signal width

compatibility issues. The following are my input and output in toplevel;

input clk,

input reset,

//inputs from low-level software (MAC/PHY) to my toplevel

input [31:0] data_in_from_ethernet,

input [1:0] data_in_from_ethernet_type,

input cpu_ip_done,

input [7:0] cpu_ip_index,

input cpu_arp_done,

input [2:0] cpu_arp_index,

//inputs exchanged to my other modules

input data_out_from_app_valid,

input [31:0] data_out_from_app,

input [31:0] dest_ip_addr,

input [15:0] dest_port,

input [15:0] data_out_from_app_length,

//outputs from low-level software (MAC/PHY) to my toplevel

output ack,

output cpu_ip_ready,

output [47:0] cpu_ip_mac,

output [31:0] cpu_ip_data,

output [7:0] cpu_ip_length,

output cpu_arp_ready,

output [47:0] cpu_arp_mac,

output [31:0] cpu_arp_data,

//outputs exchanged from my other modules

output data_in_to_app_valid,

output [31:0] data_in_to_app,

output [15:0] input_port

By default, it takes signal type as "export" and interface as "avalon_slave_0", which results in;

# 2012.04.08 23:24:40 (*) Running Generator Program for cpu_0

ERROR:

slave (toplevel_inst/avalon_slave_0) data width is 0

Error: Generator program

for module 'cpu_0' did NOT run successfully.

----------------------------------------------------------------------

I tried setting all possible options for input and output, unable to proceed especially "cpu_ip_mac"

whose width is 48 is not workingout.

Is there an option to handle this width issue?

Thanks

Liana

Error: Following DDIO Output nodes could not be placed by the Fitter

Error: DDIO Node "ddr_sdram_core:inst|ddr_sdram_component:the_ddr_sdram_component|ddr_sdram_component_auk_ddr_sdram:ddr_sdram_component_auk_ddr_sdram_inst|ddr_sdram_component_auk_ddr_datapath:ddr_io|ddr_sdram_component_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" could not be constrained to a legal location

Error: DDIO Node "ddr_sdram_core:inst|ddr_sdram_component:the_ddr_sdram_component|ddr_sdram_component_auk_ddr_sdram:ddr_sdram_component_auk_ddr_sdram_inst|ddr_sdram_component_auk_ddr_datapath:ddr_io|ddr_sdram_component_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_H[0]" could not be constrained to a legal location

Error: DDIO Node "ddr_sdram_core:inst|ddr_sdram_component:the_ddr_sdram_component|ddr_sdram_component_auk_ddr_sdram:ddr_sdram_component_auk_ddr_sdram_inst|ddr_sdram_component_auk_ddr_datapath:ddr_io|ddr_sdram_component_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|muxa[0]" could not be constrained to a legal location

Error: DDIO Node "ddr_sdram_core:inst|ddr_sdram_component:the_ddr_sdram_component|ddr_sdram_component_auk_ddr_sdram:ddr_sdram_component_auk_ddr_sdram_inst|ddr_sdram_component_auk_ddr_datapath:ddr_io|ddr_sdram_component_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ddio_bidira[0]" could not be constrained to a legal location

Error: DDIO Node "ddr_sdram_core:inst|ddr_sdram_component:the_ddr_sdram_component|ddr_sdram_component_auk_ddr_sdram:ddr_sdram_component_auk_ddr_sdram_inst|ddr_sdram_component_auk_ddr_datapath:ddr_io|ddr_sdram_component_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" could not be constrained to a legal location

Error: DDIO Node "ddr_sdram_core:inst|ddr_sdram_component:the_ddr_sdram_component|ddr_sdram_component_auk_ddr_sdram:ddr_sdram_component_auk_ddr_sdram_inst|ddr_sdram_component_auk_ddr_datapath:ddr_io|ddr_sdram_component_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|output_cell_H[0]" could not be constrained to a legal location

Error: DDIO Node "ddr_sdram_core:inst|ddr_sdram_component:the_ddr_sdram_component|ddr_sdram_component_auk_ddr_sdram:ddr_sdram_component_auk_ddr_sdram_inst|ddr_sdram_component_auk_ddr_datapath:ddr_io|ddr_sdram_component_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|muxa[0]" could not be constrained to a legal location

Error: DDIO Node "ddr_sdram_core:inst|ddr_sdram_component:the_ddr_sdram_component|ddr_sdram_component_auk_ddr_sdram:ddr_sdram_component_auk_ddr_sdram_inst|ddr_sdram_component_auk_ddr_datapath:ddr_io|ddr_sdram_component_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ddio_bidira[0]" could not be constrained to a legal location

error: following ddio output nodes could not be placed by the fitter

I am new here,and I am a chinese student.I am interested in FPGA. I hope somebody can hope me solve the problem.:)thanks.

--- Quote Start ---

error: following ddio output nodes could not be placed by the fitter

I am new here,and I am a chinese student.I am interested in FPGA. I hope somebody can hope me solve the problem.:)thanks.

--- Quote End ---

Dear 574920045,

please don't hijack other members threads.

If you want to share anything with the forum, please open you own thread and describe your matter properly.

Best regards