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Altera_Forum
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15 years ago

SOPC based PCIe design issue

Hi

I was building an SOPC based design with PCIe as a component. I instantiated the design and enabled the required clocks. After downloading the design, when i restart the computer, the computer switches OFF before starting again. I am using a DE4 board for the design. The PCIe demo provided by Terasic works fine. Any pointers as to any signals i might be missing.

The following are the signals that i have instantiated particular to pcie.

.cal_blk_clk_0(enet_refclk_50MHz),

.busy_altgxb_reconfig_pcie_compiler_0 (busy),

.fixedclk_serdes_pcie_compiler_0 (enet_refclk_125MHz),

.gxb_powerdown_pcie_compiler_0({~PCIE_PREST_n}),

.pcie_rstn_pcie_compiler_0(PCIE_PREST_n),

.pll_powerdown_pcie_compiler_0({~PCIE_PREST_n}),

.reconfig_fromgxb_pcie_compiler_0(reconfig_fromgxb),

.reconfig_togxb_pcie_compiler_0(reconfig_togxb),

.refclk_pcie_compiler_0(PCIE_REFCLK_p),

.rx_in0_pcie_compiler_0(PCIE_RX_p),

.test_in_pcie_compiler_0(test_in),

.test_out_pcie_compiler_0(test_out),

.tx_out0_pcie_compiler_0(PCIE_TX_p),

.reconfig_clk_pcie_compiler_0(enet_refclk_50MHz),

I have instantiated a altgx_reconfig core with offset_cancellation_reset input for generating the busy signal. The signal tap shows all the clocks running properly. Any idea as to why the issue might be happening.

Thanks & Regards

Hari

15 Replies

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    As far as I know SOPC won't support Gen2. It only supports gen1.

    Qsys can support up to gen2x4.

    ST interfaced one is totally different. You may have to have TLP decoder in order to use it with/in SOPC.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    What's your PCIe interface goal? Gen1/2? x1,x4, or x8? Gen1 and Gen2 requires different clock. Gen1 requires 125M and Gen1 can take 100M or 125M according pice user guide from Altera.

    I'm using Gen1 only. It sounds like we may be in same boat. Depending on compilation, I get x1 trained up link or x4 trained up link. I'm looking into SDC constraints for PCIe interface. What's your SDC constraint?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Kattice,

    In SOPC builder i was using Gen2 version. It allows only x1 data lane. I am able to get it working in Gen 2 x8 when using the Avalon ST version. Only when trying in the SOPC builder it is not working properly. If you have got it working in the SOPC builder can you share the details of the design.

    Thanks & Regards

    Hari
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hari,

    I'm using DE4 board. Which generation of PCIe are you using? Gen1/2? Also how many lanes? Which clock are you using from DE4? As for your instantiation goes, it looks correct. I'm working on Gen1 x4, but it always down trained to x1 lane. If you were able to make x1, but not x4, we are on same boat.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Can anyone suggest how to successfully get the PCIE design to work in an SOPC builder system. I am using DE4 board. I seem to be missing some connection, which i am not able to figure out.

    Regards

    Hari