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Altera_Forum's avatar
Altera_Forum
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14 years ago

SOPC based PCIe design issue

Hi I was building an SOPC based design with PCIe as a component. I instantiated the design and enabled the required clocks. After downloading the design, when i restart the computer, the comput...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

What's your PCIe interface goal? Gen1/2? x1,x4, or x8? Gen1 and Gen2 requires different clock. Gen1 requires 125M and Gen1 can take 100M or 125M according pice user guide from Altera.

I'm using Gen1 only. It sounds like we may be in same boat. Depending on compilation, I get x1 trained up link or x4 trained up link. I'm looking into SDC constraints for PCIe interface. What's your SDC constraint?