something wrong with my hold up time

hi,

In my altera's FPGA design, I see something wrong with the hold up time of dcfifo's rdptr.My schoolmate told me that this could be fixed easily by digital backend method.However,the quartus's design is finished in front-end netlist?

so how can i fix such bugs?

in addition,this bug occur in the rdclk domain,other than a cross clock domain warning.

best regards,

yang