Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Solution for a high-performance "translation" board

Hello, I'm in the very initial stages of design of a card that should do the following: * Receive data from 4-5 optical links. The data comes at ~200MBit/s per link - on a single data line...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

A viable and standard solution could be to use ASI protocol over optical interface, it supports up to 270Mbit/s per channel (it's a classical fibre channel application) and you can find ICs (Cypress, Gennum) and IPs (Altera has a complete ASI IP) for that job. In this way you won't have to design your own FW for clock and data recovery.

But indeed you may try to design your own, it is a matter of enough oversampling ratio and some FIFO-aided technique of jitter reduction. It is a very interesting experience to design a CDR block.