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Altera_Forum
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17 years ago

Solution for a high-performance "translation" board

Hello, I'm in the very initial stages of design of a card that should do the following: * Receive data from 4-5 optical links. The data comes at ~200MBit/s per link - on a single data line...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks for the detailed comment.

It surprises me that the built-in CDRs of Altera FPGAs can't handle this speed. I'm really reluctant implementing my own clock extraction in the FPGA since I have no experience with such things, but there are external CDR components that can handle such speeds and give me a clock + data, I think.