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Altera_Forum's avatar
Altera_Forum
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10 years ago

Slower input path timing if we use pins of IO 4A/7A of Cyclone V 5CGXFCC4C6F23C7 ?

Hi,

The target device we use is Cyclone V 5CGXFCC4C6F23C7.

We have problem about using pins of different IO bank as below.

Input paths timing through pins of IO bank "4A" or "7A" are worse compare to through IO bank "3A/3B/5A/5B/8A".

We found the interconnect delay from IO to first flip-flop is very slow if we use pins of IO bank 4A/7A.

Is there hardware limit or our wrong usage ?

Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    Probably you could create a simple test design with only one channel to test the input pin delay. Test this design on input pin at 4A vs 3A and etc. If with same simple design, still see input timing longer in 4A. Then this should be the hardware behavior.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    Yes, A4/7A are slower than 3A/3B/5A/5B/8A.

    For Cyclone V 5CGXFCC4C6F23C7, can we know why 4A/7A are slower ?

    Is it because there is hard IP near it ?

    Thanks.