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Honored Contributor
Honored ContributorSlower input path timing if we use pins of IO 4A/7A of Cyclone V 5CGXFCC4C6F23C7 ?
Hi, The target device we use is Cyclone V 5CGXFCC4C6F23C7. We have problem about using pins of different IO bank as below. Input paths timing through pins of IO bank "4A" or "7A...
Altera_ForumHonored Contributor
Honored ContributorHi,
Probably you could create a simple test design with only one channel to test the input pin delay. Test this design on input pin at 4A vs 3A and etc. If with same simple design, still see input timing longer in 4A. Then this should be the hardware behavior.
