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GD76's avatar
GD76
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Slow Slew Rate

How does the slow slew rate option works? In Quartus using MAX V CPLD 5ns part, in assignment editor if "SLOW SLEW RATE" is turned OFF and enabled is Yes, not timing violation. However, if turnd ON and enable is Yes or No, getting timing violation. With 4ns part, both gives no timing violation.

If "SLOW SLEW RATE" is turned OFF and enabled, shouldn't that give timing violation on slower 5ns part vs 4ns. Looks like the ON/OFF works the opposite.

  • RichardT_altera's avatar
    RichardT_altera
    4 years ago

    Hi @GD76

    May I know does my latest reply helps?

    Do you need further help regarding to this case?

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

2 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi @GD76

    A slow slew rate reduces system noise, but adds a nominal output delay to rising and falling edges. The lower the voltage standard (for example, 1.8-V LVTTL) the larger the output delay when slow slew is enabled. Each I/O pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges. If no slew-rate control is specified, the Quartus software defaults to a fast slew rate.

    For detailed functions, search for the keyword "Slew Rate" from the Device Handbook of each device and check.

    Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-v/max5_handbook.pdf

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

    • RichardT_altera's avatar
      RichardT_altera
      Icon for Super Contributor rankSuper Contributor
      4 years ago

      Hi @GD76

      May I know does my latest reply helps?

      Do you need further help regarding to this case?

      Best Regards,
      Richard Tan

      p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

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