ContributionsMost RecentMost LikesSolutionsRe: The Quartus Prime Software quit unexpectedly After removing the signal tap file from project, deleting the project.cmp.rdb file, I recreated a NEW the signal tap file. Now I can compile. Not sure why the previous STP file is the issue. It was working for a long time. Re: The Quartus Prime Software quit unexpectedly Running 18.1 for almost 9 months on Windows 10. No updates done. What I discovered is (not solution yet), removing the signal tap file and deleting the "filename.cmp.rdb", then compilation works without the Quartus quitting unexpectedly. The signal tap files worked for a week so. No change made. So not sure why yet. Re: The Quartus Prime Software quit unexpectedly How to send it through email or private chat? The Quartus Prime Software quit unexpectedly Running Quartus Standard Edition 18.1 (cannot upgrade). Always had no issue in the past but recently keep getting the message "The Quartus Prime software quit unexpectedly" whenever "Start Compilation" clicked. The design did not change. The error is Internal Error: Sub-system: SDR, File: /quartus/sld/sdr/sdr_data_session.cpp, Line: 2089 Unexpected FIO_FILE_SYSTEM::status() return Not sure what to fix. Re: NIOS programming CPLD Yes. Thanks. Please close this. Re: NIOS programming CPLD Here is my email ganesan_doraisami@waters.com Re: VHDL Error 10779 You can close this. I have global settings for VHDL 2008 compilation anyway. It turns out Quartus Std 2018 has the limitation to synthesize but 2019 Pro edition do not. Re: NIOS programming CPLD The issue is getting JAM Player Source Code to incorporate in to embedded software to read JAM file and write via JTAG. The AN425.pdf app note provide a link "Altera Jam STAPL software". Upon clicking the link, the following webpage says "Product Discontinued Notice". https://www.intel.com/content/www/us/en/support/programmable/support-resources/download/legacy-software-discontinued-notice.html NIOS programming CPLD An external MAX10 CPLD JTAG pins are connected to Cyclone V IO pins. The intent is for NIOS embedded software in Cyclone V to program the MAX10 CPLD and verify the CPLD checksum. I hear two methods like JAM and SVF. But not sure if any application or sample code exist to get me started. Not sure which method takes less memory. VHDL Error 10779 Line 434 shows the error in file spi_if.vhd. Error (10779): VHDL error at spi_if.vhd(434): expression is not constant Error (10658): VHDL Operator error at spi_if.vhd(434): failed to evaluate call to operator ""&"" Error (12152): Can't elaborate user hierarchy "spi_if:spi_if_i" Error: Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 10 warnings Error: Peak virtual memory: 4845 megabytes Error: Processing ended: Thu Feb 03 14:07:58 2022 Error: Elapsed time: 00:00:09 Error: Total CPU time (on all processors): 00:00:16 Error (293001): Quartus Prime Full Compilation was unsuccessful. 5 errors, 10 warnings I have std_logic_vector passed to create XFER_SIZE and dwitdth. Not sure why the error is.