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Altera_Forum
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10 years ago

Slip Ring Timing Issue, MAX10 PLL Problem

I'm working on the design of a rotating camera whose frame valid and pixel clock go through slip rings. We've found that there can be glitches ranging from 10 ns to 10 us on both signals. The process...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The image you've attached is too small - can't make anything out.

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Unfortunately, when I simulated this, it behaved nothing like I expected.

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What did you expect? You don't say...

Adding a 12MHz second source will not allow you to maintain a 10.519MHz output clock should inclk0 glitch/fail. The PLL only caters for one set of multiplication/division factors per clock output. So, if you need to maintain that frequency you need to provide a second 10.519MHz source.

You could generate a second output on c1 based on multiplication/division factors to suit 12MHz -> 10.519MHz. You could then use the PLL's 'activeclock' output to determine which clock is selected. Your logic would then be clocked by c0 or c1 as appropriate - which would need some careful design consideration. More likely you'll have to drive two blocks of logic - one from c0, one from c1 - and select which block's output signals to use based on 'activeclock' which would reflect the presence (or not) of your primary clock.

Cheers,

Alex