Honored Contributor
Honored ContributorThe image you've attached is too small - can't make anything out.
--- Quote Start --- Unfortunately, when I simulated this, it behaved nothing like I expected. --- Quote End --- What did you expect? You don't say... Adding a 12MHz second source will not allow you to maintain a 10.519MHz output clock should inclk0 glitch/fail. The PLL only caters for one set of multiplication/division factors per clock output. So, if you need to maintain that frequency you need to provide a second 10.519MHz source. You could generate a second output on c1 based on multiplication/division factors to suit 12MHz -> 10.519MHz. You could then use the PLL's 'activeclock' output to determine which clock is selected. Your logic would then be clocked by c0 or c1 as appropriate - which would need some careful design consideration. More likely you'll have to drive two blocks of logic - one from c0, one from c1 - and select which block's output signals to use based on 'activeclock' which would reflect the presence (or not) of your primary clock. Cheers, Alex
