Altera_Forum
Honored Contributor
11 years agosimulation with modelsim after quartus II vhdl design
Hi,
I have been wanting to verify the correct operation of my vhdl design file in quartus II (to be used on a caen v1495 VME board). I have succesfully compiled the quartus II project with the vhdl files. and then I clicked on the "RTL simulation" button to launch the modelsim software. I then simulated my current work directory and design file. After which I added 2 input signals that are required to produce an output. However how do I view or add the resultant output waveform to the wave window, so that I can test for the correct logic operations given the inputs and outputs. Thanks in advance. Kind regards.