Simulation problem with simple edge detector

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I'm trying to make sure I understand whats going on in both cases. If input goes high synchronized to the CLK it will be latched in on the next clock edge right? So, my circuit/simulation for this should work in hardware like it is?

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correct.

if INPUT is generated by same clock then there will be delay of tCO + path delay or else timing would have failed. So data for sim is best put with some delay from clk edge to match real hardware.

Generally to avoid delta delay in functional sim try generate data on clock edge rather than specific ns figures