Simulation problem with simple edge detector

Hey Kaz,

Thanks for the reply! So the delta delay is because the simulator can't do this truly in parallel so it steps through delta delays to do this? In hardware doesn't this work because at the first clock edge INPUT will go high and then the next clock edge it gets latched and the circuit will see this high signal and at this time the output goes low because it latches a 1 through the dff. Basically there is a 1 clock delay here right?

I'm trying to make sure I understand whats going on in both cases. If input goes high synchronized to the CLK it will be latched in on the next clock edge right? So, my circuit/simulation for this should work in hardware like it is?