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Altera_Forum
Honored Contributor
11 years agoThat is due to what is called delta delay.
Your logic says: elsif(rising_edge(CLK)) then input_latch <= INPUT; end if; OUTPUT <= INPUT and (not input_latch); thus input_latch acquires input at clock edhe but after delta delay. That very very small delay is seen in the comb logic of: OUTPUT <= INPUT and (not input_latch); set INPUT to '1' at 191 ns instead of 190 ns and see it disappear