(Simulation) PLL waits x number of cycles to lock

A PLL is an analog circuit, lock time varies based on PVT, PLL bandwidth, etc. There is no way to exactly predict the lock time of a PLL. Therefore, the simulation model just waits x number of cycles and just says your PLL is locked. This makes sense since most of the time you're concerned with simulating what happens in your logic after your PLL has locked.

But now I want to set the number of clock cycles for the lock signal becomes locked. Is this possible?

Thanks