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Altera_Forum
Honored Contributor
Honored Contributor(Simulation) PLL waits x number of cycles to lock
A PLL is an analog circuit, lock time varies based on PVT, PLL bandwidth, etc. There is no way to exactly predict the lock time of a PLL. Therefore, the simulation model just waits x number of cycles...
Altera_ForumHonored Contributor
Honored Contributoryes, generated your own locked signal from a counter instead of using the one from the pll (I'm sure that the pll clock is ok in simulation before the lock signal is rising).
