Simulation dprom output data 2 cycle delays

Hi,

I tried to use a 2 PORT ROM (made by the quartus 2 megafunction) but during the RTL simulation in Modelsim, the output of the ROM comes 2 cycle after the adress is sent (instead of one).

This issue was supposed to be corrected by a patch in version 11.1 of quartus

altera.co.uk/support/kdb/solutions/rd04182012_926.html (I removed the www to post it)

but I used the 12.0 version so the bug is supposed to be fixed already.

Has someone faced the same problem and come up with a solution ?

thanks

Tsarno