Simulating the Parallel Flash Loader

The PFL is NOT simulatable in RTL mode. However if you generate a gate level netlist with timing then the PFL can be simulated. Only the FPGA configuration part can be simulated NOT the Flash programming part.

If you want to simulate the configuration part of the PFL, this is possible. Create a Vector Waveform File in the Quartus II software, specify the correct input vectors and then use the Quartus II simulator to simulate the configuration. You need to understand what are the correct input vectors that will allow configuration to happen, eg the Conf_done signal must be low, nStatus must be high etc.

You can also write a model for the behavior of the FPGA config pins. This is the route I went to simulate code that does the FPGA config. The model can also be written to give a configuration error to simulate how the PFL reacts to a configuration failure if you have multiple programming images in FLASH. PFL can be set to program FPGA using 'image 1' on power-up. If 'image 1' is corrupt, PFL can move on to 'image 2'.

Hi all,

What do you mean with alone? A ModelSim simulation with a flash functional model (I used a Spansion S29GL256N model) is feasible. As said, programming can't be simulated, cause JTAG interface and programmer action aren't easily accessible, but configuration can be fully traced in simulation, you need to model FPGA nStatus and ConfigDone responses in your testbench. And there's no checking for correct configuration data, of course.

Hi,

For the flash interface part, there is a flash simulation model that comes together with AN386. You can try it out as well.

Hi,

Actually the memory model is located here.