Simulating the Parallel Flash Loader

You can also write a model for the behavior of the FPGA config pins. This is the route I went to simulate code that does the FPGA config. The model can also be written to give a configuration error to simulate how the PFL reacts to a configuration failure if you have multiple programming images in FLASH. PFL can be set to program FPGA using 'image 1' on power-up. If 'image 1' is corrupt, PFL can move on to 'image 2'.