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awaissman's avatar
awaissman
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2 years ago

Simulating F2H ACE-LITE interface on HPS.

Hello, I am finding that F2H ACE-lite interface in HPS IP have no implementation in simulation model. All outputs on this interface not driven by HPS, and after tracing in to HPS i found that nothi...
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awaissman's avatar
awaissman
Icon for New Contributor rankNew Contributor
2 years ago

Hello,

We installed support for Agilex 5, and i tried simulate this design.

After opening Platform Designer and trying generate tb i am getting following errors:

Error: agilex5_hps_f2h_simulation_intel_agilex_5_soc_0.intel_agilex_5_soc_0: "MPU CCU Clock Divider" (MPU_clk_ccu_div) 1 is out of range: Div2
Error: agilex5_hps_f2h_simulation_intel_agilex_5_soc_0.intel_agilex_5_soc_0: "MPU Peripheral Clock Divider" (MPU_clk_periph_div) 1 is out of range: Div4
Error: Generation failed with exit code 3: 2 Errors, 3 Warnings

I will try fix them on my own, but hope you can help me with this.

Thanks,