Simulating a VHDL array

Okay, here's my attempt at a testbench:

-- Test Bench for Gen_Mux
--   4-6-11
library ieee;
use ieee.std_logic_1164.all;
 
use work.pkg_array.all;
 
entity test_bench is
 generic (n: integer := 2);
end entity test_bench;
 
architecture test of test_bench is
 signal x: vec_array(0 to (2**n - 1));
 signal sel: integer range 0 to (2**n - 1);
 signal y: std_logic_vector(7 downto 0);
 
 begin
  dut: entity work.Gen_Mux(description)
   port map(
      x => x,
      sel => sel,
      y => y);
  stimulus: process is
  begin
    x(0) <= "10001001";
    x(1) <= "00001111";
    x(2) <= "11110000";
    x(3) <= "10101010";
    sel <= 2;
    wait for 5 ns;
    sel <= 0;
    wait;
  end process stimulus;
end test;

The code compiles without errors in Quartus 10.1 sp1. Does it look correct? Any suggestions?

Also, I have included this file in Assignments > Settings > EDA Tool Settings > Simulation > NativeLink Settings > Compile Test Bench..., but nothing happens when I run ModelSim-Altera. Is there another setting that I am missing somewhere?

Thanks,

Steve