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Honored Contributor
Honored ContributorSimulate cyclone iii pll with cascading counters
i had some problems when i was simulating cyclone iii pll with cascading counters.
Main settings of the are: input clock 25MHz c1 output 25kHz (25MHz / 1000) c3 output 25kHz (25MHz / 1000) i simulated this pll in questasim 6.5b and got error messages: # ** Error: (vsim-8604) D:/altera/quartus90/quartus/eda/sim_lib/altera_mf.v(11544): NaN results from division operation. ......(repeat 6 times) # ** Error: (vsim-8604) D:/altera/quartus90/quartus/eda/sim_lib/altera_mf.v(15526): NaN results from division operation. ......(repeat 6 times) # ** Error: (vsim-3601) Iteration limit reached at time 0 ps. then i modified the pll. i set c3 output 25MHz and simulated it again. I got no error messages this time but found that c1 did not work while c3 output 25MHz clock correctly. Can anyone help me?:confused:2 Replies
Altera_Forumi made a small project to test the PLL. In fact both output clock c1 and c3 works fine.
i tried to define a frequncy for c0 and c2 rescpectively, but MegaWizard said "Cannot implement the request pll Cause Post divider max count exceeded"- Altera_Forum
Does it work in synthesis? It may be helpful to define an output frequency for the first output, that can be divided to the intended low frequency. The maximum factor is 512 for Cyclone III.
