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Honored Contributor
Honored ContributorSimulate cyclone iii pll with cascading counters
i had some problems when i was simulating cyclone iii pll with cascading counters. Main settings of the are: input clock 25MHz c1 output 25kHz (25MHz / 1000) c3 output 25kHz (25MHz / 1000) ...
Altera_ForumHonored Contributor
Honored Contributori made a small project to test the PLL. In fact both output clock c1 and c3 works fine.
i tried to define a frequncy for c0 and c2 rescpectively, but MegaWizard said "Cannot implement the request pll Cause Post divider max count exceeded"
