Simulate ADC MAX10

in several tutorials and examples the reset path is connected as in the picture.

However, it doesn't work for me. if I set the reset to "true" PLL simulation does not start. If I set the reset to "false", the PLL simulation starts, however the ADC simulation does not work.

The simulation works if I disconnect PLL Reset Signal from ADC Reset Signal (platform designer), And next I assign this signal in test-bench file (with negation)

assign modular_adc_0_reset_sink_reset_n=!reset_reset_n;

My test-bench file looks like this:

initial                                                
begin                                                  
	reset_reset_n =1;
	assign modular_adc_0_reset_sink_reset_n=!reset_reset_n;
	clk_clk =0;
	#100000 
	modular_adc_0_command_valid =1;
	modular_adc_0_command_channel=0;
	reset_reset_n =0;                                                                          
end                                                    
always                                                 
#50000 clk_clk =!clk_clk;                                                 
endmodule

the simulation works, but in the downloaded examples are different. Now I don't know what is correct ??