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mmare6's avatar
mmare6
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6 years ago

Simulate ADC MAX10

in several tutorials and examples the reset path is connected as in the picture. However, it doesn't work for me. if I set the reset to "true" PLL simulation does not start. If I set the rese...
mmare6's avatar
mmare6
Icon for New Contributor rankNew Contributor
6 years ago

I found that the platform designer generates such code

adcSys_modular_adc_0 modular_adc_0 (
		.clock_clk              (clk_clk),                              //          clock.clk
		.reset_sink_reset_n     (~rst_controller_reset_out_reset),   // this reset negation

Platform Designer generate code with reset negation in ADC instance. Is possible edit this??

When I manually remove "~" compiler generate error:

Error (10228): Verilog HDL error at adcsys.v(6): module "adcSys" cannot be declared more than once