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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Simple RAM test, with unexplained clock delay?

Hi,

I'm creating a scanline buffer, which will eventually be filled by a fast clock, and which will be read by a slower clock (VGA clock).

But before I'm there yet, I decided to do a simple RAM test.

I have a RAM module (the scanline buffer), consisting of 640 words of 12 bits. For this test, I am constantly reading bit0 of the first 8 words, and combining these 8 bits to the 8bit led buffer, which feeds LEDG, so I can see this buffer visually. I'm also using switches to drive the write enable, write address and write data.

The problem now is that when I write a 1 to address 0, LEDG[1] will light up, while I expected LEDG[0] to light up :(. It seems like there is a single clock delay which I can't explain.

Maybe someone can help me understand why this happens?

I've attached my Verilog test files to this thread so you can see for yourself.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    There is a one clock latency on reading the RAM. The read address is latched on one clock with the read data being available on the following clock:

    Change this: 

    always @(posedge clk)
	begin
		if (reset)
		begin
			rdx = 0;
		end
		else
		begin
			ledbuffer = rddata;
			rdx = rdx+3'b1;
		end
	end

    to this: 

    
reg  rdx_r;
always @(posedge clk or posedge reset)
    if (reset) begin
            rdx     <= 3'd0;
            rdx_r  <= 3'd0;
    end else begin
	    ledbuffer <= rddata;
	    rdx     <= rdx+3'd1;
            rdx_r  <= rdx;
    end