Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Simple RAM test, with unexplained clock delay?

Hi, I'm creating a scanline buffer, which will eventually be filled by a fast clock, and which will be read by a slower clock (VGA clock). But before I'm there yet, I decided to do a simp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

There is a one clock latency on reading the RAM. The read address is latched on one clock with the read data being available on the following clock:

Change this: 

always @(posedge clk)
	begin
		if (reset)
		begin
			rdx = 0;
		end
		else
		begin
			ledbuffer = rddata;
			rdx = rdx+3'b1;
		end
	end

to this: 


reg  rdx_r;
always @(posedge clk or posedge reset)
    if (reset) begin
            rdx     <= 3'd0;
            rdx_r  <= 3'd0;
    end else begin
	    ledbuffer <= rddata;
	    rdx     <= rdx+3'd1;
            rdx_r  <= rdx;
    end