Signed operators in Verilog

Hello again everybody,

I am trying to build a PID controller using Verilog signed operators,

some up to 32 bits wide. Quartus II is doing some very strange things

to my code however, removing bits inside the bus and so on.

What do I need to watch out for when using signed operators inside Quartus ?

What is the size limitation for a signed register or port ?

Thanks a bunch !!

Cheers,

Eric