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Honored Contributor
Honored ContributorSigned operators in Verilog
Hello again everybody,
I am trying to build a PID controller using Verilog signed operators, some up to 32 bits wide. Quartus II is doing some very strange things to my code however, removing bits inside the bus and so on. What do I need to watch out for when using signed operators inside Quartus ? What is the size limitation for a signed register or port ? Thanks a bunch !! Cheers, Eric1 Reply
Altera_Forumare you getting the correct results? when multiplying by a constant, the synthesizer will optimize the multiplier which may remove some of the logic.
