Forum Discussion
Altera_Forum
Honored Contributor
9 years agoIn case anyone else stumbles upon this thread looking for answers, I figured out my problem. I needed to reduce the JTAG clock rate from 24 MHz to 6 MHz. I'm still unsure why I was able to program the FPGA and run the JTAG scan tests successfully at 24 MHz. I would have expected those operations to fail as well.