signal tap - question

Cool thanks for the quick explanation yeah i dont know why that 'export' feature was even 'on' considering there are no partitions defined - although my design block is not is the top of the fpga - we have a very small team and the top code is never going to be used in netlist format in another design somewhere. So dont know why that was enabled when i got it, but do appreciate your help, esp since now I know and will try turning back on incremental compile to make ST easier to reconfigure, just as long as the 'export' option is 'off'.