signal tap - question

I appreciate the swift response, being not so familiar with quartus it would appear that the solution then from the handbook and qi51015 would be either to turn off the incremental compile feature, or will i have to do this and also go into the design partition planner and do a "remove from parent" on the submodule i wish to use the Signal Tap interface on? Im not trying to build the final design, just want to test my block in the hw.

Update: I still really dont understand what a "exported design partition" but if im to use a pre-synthesis node i believe i have to give up on incremental compiles completely correct? At least thats what my testing and experimentation has shown so far.

I tried messing around and removing my block that has the ST taps from the parent top block diagram shown under the 'design partition planner' (in 9.1sp1) but my design still error'd out with same error. However when i disabled the incremental compile it seemed to go through and build successfully with ST (albeit not tested yet).

So i guess the final question is what exactly is a "export project" and can i still go back and turn on incremental compile and just disable this "export project" setting, and still get it to build successfully?