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xianghua_li's avatar
xianghua_li
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1 year ago

Signal bvalid of Agilex HPS is too slow when Rtile BAM writes to CCU through f2h_bridge

Following document [Intel Agilex® 7 FPGA I-Series PCIe Root Port Reference Design | Documentation | RocketBoards.org] (Intel Agilex® 7 FPGA I-Series PCIe Root Port Reference Design | Documentation | ...
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Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.