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Altera_Forum
Honored Contributor
14 years agoThis is the architecture code:
... architecture mul_four of mul_four is signal n1: sfixed (4 downto -4); signal n2: sfixed (n1'high + 1 downto n1'low); signal n3: ufixed (5 downto -4); signal u: ufixed (5 downto -4); begin n1 <= to_sfixed(-0.129,n1); n2 <= abs(n1); n3 <= ufixed(n2); process(clk) begin if (clk'event and clk='1') then for i in 0 to 3 loop out_A(i) <= (to_ufixed (A(i),u)) * n3; end loop; end if; end process; end mul_four; I have simulate in ModelSim and the output seem like correct. I just want to confirm,do I convert the sfixed to ufixed in the right way?..thanks for helps