sfixed to ufixed conversition

I write the code below and its work;

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Library ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

ENTITY try IS

PORT(

y : IN sfixed(4 downto -4);

Clock : IN STD_LOGIC;

alphaEstOut : OUT ufixed(5 downto -4));

END try;

ARCHITECTURE Behavior OF try IS

SIGNAL aa : sfixed(y'high +1 downto y'low);

BEGIN

PROCESS(Clock)

BEGIN

IF rising_edge(Clock) THEN

aa<=abs(y);

alphaEstOut<=ufixed(aa);

END IF;

END PROCESS;

END Behavior;