sfixed to ufixed conversition

you cant really do that, because ufixed is unsigned fixed, and sfixed is signed fixed.

Therefore, using a ufixed to size an sfixed is not appropriate. and direct conversion from sfixed to ufixed would be innapropriate without an abs function.

so, dont put signed numbers into ufixed. Keep them sfixed.

Sorry for the miss typing; signal n1: sfixed (4 downto -4);

How can I convert the sfixed to ufixed using abs function? Can you give any links or note on abs function to study..thanks for reply

I write the code below and its work;

-------------------------------------------------------------

Library ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

ENTITY try IS

PORT(

y : IN sfixed(4 downto -4);

Clock : IN STD_LOGIC;

alphaEstOut : OUT ufixed(5 downto -4));

END try;

ARCHITECTURE Behavior OF try IS

SIGNAL aa : sfixed(y'high +1 downto y'low);

BEGIN

PROCESS(Clock)

BEGIN

IF rising_edge(Clock) THEN

aa<=abs(y);

alphaEstOut<=ufixed(aa);

END IF;

END PROCESS;

END Behavior;

Now, I proceed to next stage which is multiply the conversion output with ufixed values (input).

library ieee;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

package my_data_types is

type vector is array (natural range <>) of integer;

type ufixed_array_t is array (0 to 3) of ufixed (9 downto -10);

end my_data_types;

library ieee;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

use work.my_data_types.all;

entity mul_four is

port (clk: in bit;

A: in vector (0 to 3);

out_A: out ufixed_array_t);

end mul_four;

architecture mul_four of mul_four is

signal n1: sfixed (4 downto -4);

signal n2: sfixed (n1'high + 1 downto n1'low);

signal n3: ufixed (5 downto -4);

signal u: ufixed (5 downto -4);

begin

process(clk)

begin

if (clk'event and clk='1') then

n1 <= to_sfixed(-0.129,n1);

n2 <= abs(n1);

n3 <= ufixed(n2);

end if;

for i in 0 to 3 loop

out_A(i) <= (to_ufixed (A(i),u)) * n3;

end loop;

end process;

end mul_four;

There are no error when I compile in quartus, but then an error occur in ModelSim:# Cannot continue because of fatal error. ( at line 36).

Can anyone check my code?..do I write in wrong way?..need helps

you've got the sizing wrong.

(5 downto -4) * (5 downto -4) would give you a (11 downto -8) result.

out_A(i) is (9 downto -10), so it doesnt fit properly. BUT there are the correct number of bits, so you effectivly just divided the result by 4.

Secondly - you cannot put the loop outside of the clock branch. Move the for loop into the clocked bit of the process.

This is the architecture code:

...

architecture mul_four of mul_four is

signal n1: sfixed (4 downto -4);

signal n2: sfixed (n1'high + 1 downto n1'low);

signal n3: ufixed (5 downto -4);

signal u: ufixed (5 downto -4);

begin

n1 <= to_sfixed(-0.129,n1);

n2 <= abs(n1);

n3 <= ufixed(n2);

process(clk)

begin

if (clk'event and clk='1') then

for i in 0 to 3 loop

out_A(i) <= (to_ufixed (A(i),u)) * n3;

end loop;

end if;

end process;

end mul_four;

I have simulate in ModelSim and the output seem like correct. I just want to confirm,do I convert the sfixed to ufixed in the right way?..thanks for helps