sfixed to ufixed conversition

Now, I proceed to next stage which is multiply the conversion output with ufixed values (input).

library ieee;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

package my_data_types is

type vector is array (natural range <>) of integer;

type ufixed_array_t is array (0 to 3) of ufixed (9 downto -10);

end my_data_types;

library ieee;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

use work.my_data_types.all;

entity mul_four is

port (clk: in bit;

A: in vector (0 to 3);

out_A: out ufixed_array_t);

end mul_four;

architecture mul_four of mul_four is

signal n1: sfixed (4 downto -4);

signal n2: sfixed (n1'high + 1 downto n1'low);

signal n3: ufixed (5 downto -4);

signal u: ufixed (5 downto -4);

begin

process(clk)

begin

if (clk'event and clk='1') then

n1 <= to_sfixed(-0.129,n1);

n2 <= abs(n1);

n3 <= ufixed(n2);

end if;

for i in 0 to 3 loop

out_A(i) <= (to_ufixed (A(i),u)) * n3;

end loop;

end process;

end mul_four;

There are no error when I compile in quartus, but then an error occur in ModelSim:# Cannot continue because of fatal error. ( at line 36).

Can anyone check my code?..do I write in wrong way?..need helps