Several little questions about VHDL and its simulation wave

I am working on VHDL,I have got some questions.

1.what does the wave form ,that is just a vertical line and lasted for no-time,mean? In my work that signals still worked in sequencial case,seeming not to consider the tsu and th parameters.That's confusing.

2.Does the output signal affect its inner signals? The output signal was just assigned somewhere in the codes,but not control anything.In my work, inner signals wave form would change if I change the place of assignment of output signal.That's what I cannot understand.

3.If I use this type of program shown below,the action to the conctrol signal should happen in the next clock edge.,not the current edge,am I right?

......

1:process(...) begin control<='0'...--reset control signal

......control<='1';--assign it somewhere in clock edge

end process;

2:process(...)begin if rising_edge(clk) and control='1' then ...--action

Thanks for your attention.