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Honored Contributor
Honored ContributorSeveral little questions about VHDL and its simulation wave
I am working on VHDL,I have got some questions. 1.what does the wave form ,that is just a vertical line and lasted for no-time,mean? In my work that signals still worked in sequencial case,seeming...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 3.If I use this type of program shown below,the action to the conctrol signal should happen in the next clock edge.,not the current edge,am I right? ...... 1:process(...) begin control<='0'...--reset control signal ......control<='1';--assign it somewhere in clock edge end process; 2:process(...)begin if rising_edge(clk) and control='1' then ...--action --- Quote End --- Yes, the action to the conctrol signal should happen in the next clock edge
