Several little questions about VHDL and its simulation wave

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3.If I use this type of program shown below,the action to the conctrol signal should happen in the next clock edge.,not the current edge,am I right?

......

1:process(...) begin control<='0'...--reset control signal

......control<='1';--assign it somewhere in clock edge

end process;

2:process(...)begin if rising_edge(clk) and control='1' then ...--action

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Yes, the action to the conctrol signal should happen in the next clock edge