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Altera_Forum's avatar
Altera_Forum
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16 years ago

Several little questions about VHDL and its simulation wave

I am working on VHDL,I have got some questions. 1.what does the wave form ,that is just a vertical line and lasted for no-time,mean? In my work that signals still worked in sequencial case,seeming...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Postpoint:I lost some points.Half of time for the control signal take effect in the rising edge of current clock, while the other half lasted for a period doing nothing.

Sorry for that.