Setup slack on generated clock of SDRAM.

Output clocks should have false path timing exceptions on them. The failed analysis you are seeing (that screenshot is way too small; can hardly read anything in it) is as if the output is a data path, which it isn't.

As such, you also don't need the set_min_delay and set_max_delay constraints. This is a clock, so it is used as a reference for clocking the external device, not for meeting path delay in the FPGA.

Is $pll_pin0 the input reference clock of the PLL or the output clock pin? It should be the output pin. And you should not have the duty_cycle option in there either. Just do a derive_pll_clocks instead which handles the creation of both output clocks from the PLL. So you should have after all this (assuming $pll_pin0 is the output clock pin of the PLL for clk_sdram):

create_clock -period <period> -name <input clock name> [get_port <input clock port>]

derive_pll_clocks

create_generated_clock -name clk_sdram -source [get_pins $pll_pin0] [get_ports {sdram_clk_pad_o}]

set_false_path -to [get_ports {sdram_clk_pad_o}]

Let me know if that helps.

#iwork4intel