Serial Flash Controller II Intel FPGA IP and Nios II connection

Hello

I am using EP4CGX150CF23C8 connected to EPCQ128ASI16N flash at ASx1 mode.

Connection designed by Platform designer at following mode:

Clock in that used by CPU (Nios II processor) is 100Mhz.

As maximum frequency to Serial Flash Controller is 50Mhz - the clock to the Flash controller connected from the PLL's output (50Mhz).

Data and instructions busses of the Serial Flash Controller connected to the Nios through 100Mhz Avalon busses directly without any crossing bridge.

After project compilation I get warning 15064:

This warning related to ALTERA_DCLK_OBUF (DCLK of serial flash) feeds by 50Mhz from PLL.

No action related to PLL help to get rid of this warning (changing PLL's, PLL's output).

The only thing that helps is to define Clock Source as 50Mhz and connect it both to the Nios and to the flash.

But I want to run Nios at 100Mhz so it is not a solution for me.

I have 2 questions:

1. Is it ok to connect Serial Flash Controller II Intel FPGA IP as I did - directly to the Avalon busses without crossing bridge and to connect clock to the PLL's output? Or I can encounter a clock domain issues?

2. What should be done to get rid of the warning 15064? Or I can simply ignore it?

Thank you

Alex

Thank you

Alex