Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Serial backplane protocols

Hi,

I'm looking for some inspiration here:

I have a set of point to point backplane links between a central Arria FPGA on one card and a number of Cyclone devices (all on separate cards).

On each link, there are 2 LVDS pairs in the Tx direction (bit clock and data), and in the Rx direction there is a single LVDS pair for data. The idea is to use DPA on the Rx side (which will be frequency locked wrt the Tx). I don't need a huge bandwidth - 150MHz SDR would probably suffice. The hardware is fairly fixed but I can influence the design to a certain degree.

My question is, what standard and not too complex protocols are there out there which would make implementation of this link straightforward. I don't want to re-invent the wheel by having to write masses of complicated firmware and I don't want the software having to care too much about the link either. The Cyclones will be on the smaller end of the scale. I can't afford to have Ethernet LAN chips or anything like that. Also, CRC error detection is a requirement. I'm not sure if I need to worry about retries if an error occurs. To be honest, if an error occurs it is probably because a card isn't plugged in correctly i.e. detecting errors is probably more important because the user will probably have to do something to rectify the problem.

And I'm not too well informed on serial protocols, so any advice would be appreciated.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    If I understand right, your protocol question is aiming at the data link layer. It involves frame structure, frame sync and error detection.

    In part, the protocol decision depends on your communication structure, e.g. if packets of constant size are transmitted with fixed rate or some kind of adressing or variable packet structure is intended. A simple option is to divide down the clock to make it act as frame/word sync. An unique sync word would be required in addition to mark a packet boundary.

    As a side remark, in the lower data rate domain up to 100 or possibly 200 MBPS, data links can also work over a single differential pair for each direction, using asynchronous or synchronous serial transmission and oversampling at the RX side. Combined with 8b/10b coding, also ethernet-like transformer coupled physical layers can be used.