SERDES in Stratix II

Only the side banks LVDS pins have SERDES blocks in the IOE. The top / bottom LVDS clock input pins don’t have SERDES blocks. The side bank clock pins are a little different. Some of them are dedicated clock pins to the PLLs / global lines. They do not have SERDES. Some of the clock pins on the side banks have dual purpose, so they can be used as receiver channels or clock inputs I believe. You can tell which ones are which by looking at which ones support differential termination. The ones that do support diff term are the dual purpose ones. You should be able to see a SERDES block next to them in the floor planner. The clocks without diff term have no SERDES blocks. The top / bottom clock pins don’t have diff term or SERDES blocks.

In Stratix and Stratix II devices, how come there are not VCCIO pins for I/O banks 9 - 12?

In Stratix and Stratix II mcse (http://www.test-inside.com) devices, how come there are not VCCIO pins for I/O banks 9 - 12?

As I look at the Stratix II GX pinout file, it seems like bank 9-12 are only for PLL IO which was driven by VCC_PLL*_OUT. I believe this is why there is no VCCIO for these banks.