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Altera_Forum
Honored Contributor
Honored ContributorSelf reset to FPGA
Hi, I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Co...
Altera_ForumHonored Contributor
Honored ContributorThe problem of internal reset controllers or "self-reset" has been previously discussed. My conclusion is that you can generate a synchronously released reset signal by an internal reset generator with sufficient metastability MTBF. I'm using the method in a number of production designs where the hardware guys didn't provide a hardware reset signal.
http://www.alteraforum.com/forum/showthread.php?t=6067 http://www.alteraforum.com/forum/showthread.php?t=6621 http://www.alteraforum.com/forum/showthread.php?t=18591 The essential point in the metastability analysis is (if I remember the previous discussion right) that possible metastable events (= POR release violating clock setup/hold requirements) in the reset counter can't occur for all counter bits simultaneously, so you can caculate with multi-register MTBF.
