SDRAM without HPS

Few things I notice.

You don't cover in your code if waitrequest is high. You have to continue holding the address and control signals when this happens. It might be easier to make use of some off the shelf component in Platform Designer instead of exporting the interface and coding your own Avalon host to communicate with the SDRAM. Maybe a FIFO or something from the IP Catalog.

For Signal Tap, use the pre-synthesis Signal Tap filter when tapping nodes. That way you'll recognize the signals from the code instead of the changed names you'll see if you use the post-fit filter.

Also, I presume you have a .sdc file with timing constraints and that you made pin assignments correctly in the Pin Planner.